Field of the Invention
The present invention relates to a semiconductor device and more particularly to a technology to improve performance of a switching device.
Description of the Background Art
In recent times, intelligent power modules (IPMs) are adopted to achieve energy-conservation, miniaturization, and weight reduction of household electrical appliances. For switching devices in the IPMs, insulated gate bipolar transistors (IGBTs) are widely used.
The IGBTs are required to be devices having low on-resistance, low switching loss, and high durability.
A guarantee of use in high current density and of operation in 150° C. or more is required recently, thereby requiring the IGBTs having durability higher than the conventional ones.
Examples of modes in which a malfunction occurs in the device include a latch-up mode. The latch-up mode that damages the device is resulted from a latch-up state where the current keeps flowing. The latch-up state is an on-state of a parasitic thyristor. This is caused by a situation in which a voltage drop due to a hole current flowing through a P-type base layer exceeds a built-in voltage between an emitter layer having a relatively high concentration (N+) of N-type impurities and the P-type base layer when the IGBT, for example, is shifted from an on-state where a main current flows to an off-state where no main current flows.
To increase a tolerance to the latch-up, the resistance of the base layer and the voltage drop upon the hole current flowing through the base layer need to be reduced. The built-in voltage decreases in high temperature operation, so that the latch-up mode easily occurs and the durability decreases.
To solve this problem, Japanese Patent Application Laid-Open No. 2001-308328 discloses the technology to reduce the resistance of the base layer by forming a diffusion layer having a relatively high concentration (P+) of P-type impurities deeper than the emitter layer in the IGBT having a trench gate and to prevent the parasitic thyristor from turning on by passing the hole built up in the device during turn-off to the emitter layer to secure high durability.
The configuration disclosed in Japanese Patent Application Laid-Open No. 2001-308328 forms the diffusion layer deeper than the emitter layer, the diffusion layer having a high concentration of the P-type impurities necessary for securing the durability. In this case, however, the diffusion layer gets close to a channel region near the trench gate. As a result, electrical characteristics of the semiconductor device are affected, and thus the electrical characteristics such as a threshold voltage vary greatly.